Multi-spectral Satellite Image Processing on a Platform FPGA Engine

Multi-spectral satellite image sets present a storage and transmission problem. These image sets can also contain line features that typical detection methods do not resolve sharply enough for some purposes. The Karhunen-Loève transform (KLT) presents a solution to both these problems. Firstly, the KLT can be used as a form of lossy data compression, only retaining the higherorder images in the transformed set, as these contain the significant features. The KLT can also substitute as a coder of wavelet transform coefficients, equally for the purposes of compression. Secondly, when an image contains buildings then one technique is to use a KLT in order to highlight these features. The KLT can also provide a characteristic signature of differing regions in multi-spectral imagery and unlike 2D methods prior image fusion is not required. However, the KLT’s kernel is data-dependent unlike related orthogonal transforms. In other words, it has to be re-calculated for each image set to which it is applied. This causes a computational bottleneck when batches of satellite images are processed. Neither conventional uniprocessors or medium-grained parallel machines are well-matched to KLT processing, either calculation of the kernel or subsequent application of the transform to the image set data. This is because the KLT exhibits fine-grained parallelism in two of its three processing stages. An intermediate third stage of the KLT can be mapped to a RISC processor or an ASIC. In contrast to other architectures, a platform FPGA may be viewed as a fine-grained parallel-processing architecture. Pipelining of the image sets is then required to overlap data streaming with computation. Based on a prototype KLT engine, this paper demonstrates that the prototype design can be incrementally scaled to provide real-time processing of satellite image sets, either for the purposes of compression or feature extraction. Further replication of FPGAs to form a KLT engine allows single-pass processing for medium-sized image sets without the need for repeated data streaming. Each FPGA-based KLT could form a ’System-on-Chip’. The result is incrementally scalable to a desired performance. The design has been targeted at Xilinx Virtex series FPGAs, and the prototype produced through Celoxica’s DK environment and Handel-C hardware compiler.